The present invention relates to equalizers such as are used in data receivers.
Much of today's data communication equipment, such as high speed voiceband data sets (modems), are comprised of high-density integrated circuits (ICs). The cost of designing and developing such ICs is relatively high. It is thus desirable that a particular IC design be able to be incorporated into a line of products rather than just a single product, thereby distributing the design and development costs over the entire line. The above considerations apply, in particular, to equalizers which are used in voiceband data sets to correct for channel-induced distortion, such as intersymbol interference. In the usual such equalizer, a predetermined number of previously-formed samples of a received data signal, referred to as line samples, are multiplied by respective ones of an ordered plurality, or queue, of coefficients and the resulting products are summed to form the equalizer output.
In designing an equalizer which can be used in more than one data set type, account must be taken of the fact that the length of the equalizer (i.e., the number of line samples (or coefficients) which are used to form each equalizer output) may differ for data sets operating at, for example, different bit rates. Advantageously, the requirement of different equalizer lengths can be accommodated by designing an equalizer IC which can be used as a modular building block, with two or more such "equalizer sections" being interconnected in series to provide an overall equalizer of the desired length. A further advantage of this building block approach is that the equalizer sections, or series connections of same, can be arranged in parallel to provide a so-called fractionally spaced equalizer.